31 #ifndef MSHADOW_TENSOR_H_ 32 #define MSHADOW_TENSOR_H_ 63 inline std::ostream &operator<<(std::ostream &os, const Shape<ndim> &shape);
69 template<
int dimension>
72 static const int kDimension = dimension;
74 static const int kSubdim = dimension - 1;
82 for (
int i = 0; i < kDimension; ++i) {
83 this->shape_[i] = s[i];
108 for (
int i = 0; i < kDimension; ++i) {
109 if (s.
shape_[i] != this->shape_[i])
return false;
118 return !(*
this == s);
135 s.
shape_[1] = this->shape_[kDimension - 1];
138 for (
int i = 0; i < kDimension - 1; ++i) {
139 ymax *= this->shape_[i];
146 index_t size = this->shape_[0];
148 for (
int i = 1; i < kDimension; ++i) {
149 size *= this->shape_[i];
161 for (
int i = dimstart; i < dimend; ++i) {
162 num *= this->shape_[i];
174 for (
int i = 0; i < kSubdim; ++i) {
175 s.
shape_[i] = this->shape_[i + 1];
185 template<
int dimstart,
int dimend>
187 Shape<dimend - dimstart> s;
189 for (
int i = dimstart; i < dimend; ++i) {
190 s[i - dimstart] = this->shape_[i];
196 friend std::ostream &operator<<(std::ostream &os, const Shape<dim> &shape);
230 s[0] = s0; s[1] = s1; s[2] = s2;
244 s[0] = s0; s[1] = s1; s[2] = s2; s[3] = s3;
259 s[0] = s0; s[1] = s1; s[2] = s2; s[3] = s3; s[4] = s4;
272 switch (src_layout) {
282 LOG(FATAL) <<
"Invalid layout for 3d shape " << src_layout;
284 switch (dst_layout) {
295 LOG(FATAL) <<
"Invalid layout for 3d shape " << src_layout;
309 switch (src_layout) {
320 LOG(FATAL) <<
"Invalid layout for 4d shape " << src_layout;
324 switch (dst_layout) {
334 LOG(FATAL) <<
"Invalid layout for 4d shape " << src_layout;
349 switch (src_layout) {
361 LOG(FATAL) <<
"Invalid layout for 5d shape " << src_layout;
364 switch (dst_layout) {
375 LOG(FATAL) <<
"Invalid layout for 5d shape " << src_layout;
383 template<
typename Device>
409 template<
typename Container,
typename Device,
int dimension,
typename DType>
419 template<
typename Device,
int dimension,
422 Device, dimension, DType> {
430 static const int kSubdim = dimension - 1;
435 DType *dptr_ =
nullptr;
455 : shape_(shape), stream_(NULL) {}
458 : dptr_(dptr), shape_(shape), stride_(shape[kSubdim]), stream_(NULL) {}
462 : dptr_(dptr), shape_(shape), stride_(shape[kSubdim]), stream_(stream) {}
467 : dptr_(dptr), shape_(shape), stride_(stride), stream_(stream) {}
473 this->stream_ = stream;
479 template<
int startdim>
483 for (
int i = startdim; i < kSubdim; ++i) {
484 memsz *= this->shape_[i];
493 return this->shape_[dimension - 1] == stride_;
499 return this->MemSize<0>();
530 shape_.
SubShape(), stride_, stream_);
543 s, stride_, stream_);
555 template<
typename E,
int etype>
558 return this->__assign(exp);
562 return this->__assign(exp);
568 template<
typename Device,
typename DType>
570 public TRValue<Tensor<Device, 1, DType>, Device, 1, DType> {
579 : shape_(shape), stream_(NULL) {}
581 : dptr_(dptr), shape_(shape), stride_(shape[0]), stream_(NULL) {}
583 : dptr_(dptr), shape_(shape), stride_(shape[0]), stream_(stream) {}
586 : dptr_(dptr), shape_(shape), stride_(stride), stream_(stream) {}
588 this->stream_ = stream;
625 template<
typename E,
int etype>
628 return this->__assign(exp);
631 return this->__assign(exp);
644 template<
typename Device>
652 template<
typename Device>
659 template<
typename Device>
669 template<
typename Device>
671 bool create_dnn_handle,
677 template<
typename Device>
679 return NewStream<Device>(
true,
false, dev_id);
685 template<
typename Device>
698 template<
int dim,
typename DType>
712 template<
int dim,
typename DType>
721 template<
int dim,
typename DType>
729 template<
int dim,
typename DType>
743 template<
typename Device,
typename DType,
int dim>
756 template<
int dim,
typename DType>
768 template<
int dim,
typename DType>
780 template<
int dim,
typename DType>
792 template<
int dim,
typename DType>
801 template<
typename DType>
808 template<
typename DType>
817 template<
typename DType>
827 template<
typename DType>
839 template<
bool clip = true,
typename IndexType,
typename DType>
851 template<
bool clip = true,
typename IndexType,
typename DType>
864 template<
typename IndexType,
typename DType>
878 template<
typename IndexType,
typename DType>
891 template<
typename IndexType,
typename DType>
903 template<
typename IndexType,
typename DType>
913 template<
typename KDType,
typename VDType>
915 bool is_ascend =
true);
922 template<
typename KDType,
typename VDType>
924 bool is_ascend =
true);
933 template<
typename Device,
typename VDType,
typename SDType>
950 template<
typename Saver,
typename R,
int dim,
951 typename DType,
typename E,
int etype>
966 template<
typename Saver,
typename R,
int dim,
967 typename DType,
typename E,
int etype>
983 template<
typename Saver,
typename Reducer,
984 typename R,
typename DType,
typename E,
int etype>
1001 template<
typename Saver,
typename Reducer,
typename R,
1002 typename DType,
typename E,
int etype>
1020 template<
typename Saver,
typename Reducer,
int dimkeep,
1021 typename R,
typename DType,
typename E,
int etype>
1039 template<
typename Saver,
typename Reducer,
int dimkeep,
1040 typename R,
typename DType,
typename E,
int etype>
1050 template<
typename Device,
typename DType>
1063 template<
bool transpose_left,
bool transpose_right,
typename Device,
typename DType>
1081 #ifdef MSHADOW_SCALAR_ 1082 #error "MSHADOW_SCALAR_ must not be defined" 1085 #define MSHADOW_SCALAR_ float 1087 #undef MSHADOW_SCALAR_ 1088 #define MSHADOW_SCALAR_ double 1090 #undef MSHADOW_SCALAR_ 1091 #define MSHADOW_SCALAR_ int32_t 1093 #undef MSHADOW_SCALAR_ 1094 #define MSHADOW_SCALAR_ int64_t 1096 #undef MSHADOW_SCALAR_ 1097 #define MSHADOW_SCALAR_ mshadow::half::half_t 1099 #undef MSHADOW_SCALAR_ 1100 #endif // MSHADOW_TENSOR_H_ void VectorDot(Tensor< Device, 1, DType > dst, const Tensor< Device, 1, DType > &lhs, const Tensor< Device, 1, DType > &rhs)
CPU/GPU: 1 dimension vector dot.
Definition: tensor_cpu-inl.h:598
void FreeSpace(Tensor< cpu, dim, DType > *obj)
CPU/GPU: free the space of tensor, will set obj.dptr to NULL.
Definition: tensor_cpu-inl.h:141
Stream< Device > * stream_
Definition: tensor.h:575
MSHADOW_XINLINE index_t & operator[](int idx)
get corresponding index
Definition: tensor.h:91
void IndexFill(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Fill the values of the destination matrix to specific rows in the source matrix...
Definition: tensor_cpu-inl.h:548
void SoftmaxGrad(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 2, DType > &src, const Tensor< cpu, 1, DType > &label)
CPU/GPU: softmax gradient.
Definition: tensor_cpu-inl.h:307
PaddingExp< SrcExp, DType, ExpInfo< SrcExp >::kDim > pad(const Exp< SrcExp, DType, etype > &src, index_t pad)
padding expression, pad a image with zeros on boundaries, padding affects shape[0], and shape[1]
Definition: pad.h:72
MSHADOW_XINLINE index_t Size(void) const
Definition: tensor.h:145
DType * dptr_
pointer to the data
Definition: tensor.h:435
Tensor RValue, this is the super type of all kinds of possible tensors.
Definition: tensor.h:410
Stream< Device > * NewStream(bool create_blas_handle, bool create_dnn_handle, int dev_id=-1)
create a new stream from system
MSHADOW_XINLINE Shape< dimend-dimstart > Slice(void) const
slice the shape from start to end
Definition: tensor.h:186
MSHADOW_XINLINE Tensor< Device, 2, DType > FlatTo2D(void) const
Definition: tensor.h:593
void Copy(Tensor< cpu, dim, DType > dst, const Tensor< cpu, dim, DType > &src, Stream< cpu > *stream=NULL)
copy data from one tensor to another, with same shape
Definition: tensor_cpu-inl.h:146
void ShutdownTensorEngine(void)
Shutdown tensor engine on current device this function should be called after all GPU tensor operatio...
shape of a tensor
Definition: tensor.h:54
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape, Stream< Device > *stream)
Definition: tensor.h:582
void MapExp(TRValue< R, cpu, dim, DType > *dst, const expr::Exp< E, DType, etype > &exp)
CPU/GPU: map a expression to a tensor, this function calls MapPlan.
Definition: tensor_cpu-inl.h:208
Definition: stream_gpu-inl.h:38
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape)
constructor from data pointer and shape, without stride
Definition: tensor.h:457
MSHADOW_XINLINE Tensor< Device, 1, DType > FlatTo1D(void) const
flatten the tensor to 1 dimension
Definition: tensor.h:513
Shape< dimension > shape_
shape of the tensor
Definition: tensor.h:437
MSHADOW_XINLINE const DType & operator[](index_t idx) const
Definition: tensor.h:613
MSHADOW_XINLINE Shape< 4 > Shape4(index_t s0, index_t s1, index_t s2, index_t s3)
construct a four dimension shape, stride will equal s0
Definition: tensor.h:241
MSHADOW_XINLINE bool operator!=(const Shape< kDimension > &s) const
Definition: tensor.h:117
void SortByKey(Tensor< cpu, 1, KDType > keys, Tensor< cpu, 1, VDType > values, bool is_ascend=true)
CPU/GPU: Sort key-value pairs stored in separate places. (Stable sort is performed!) ...
Definition: tensor_cpu-inl.h:559
Tensor< Device, dimension, DType > & operator=(const expr::Exp< E, DType, etype > &exp)
functions to fit expression template
Definition: tensor.h:557
MSHADOW_XINLINE Shape< 2 > FlatTo2D(void) const
Definition: tensor.h:133
void Softmax(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 2, DType > &energy)
CPU/GPU: normalize softmax: dst[i][j] = exp(energy[i][j]) /(sum_j exp(energy[i][j])) ...
Definition: tensor_cpu-inl.h:484
void VectorizedSort(Tensor< Device, 1, VDType > values, Tensor< Device, 1, SDType > segments)
CPU/GPU: Sort the keys within each segment. (Stable sort is performed!) Segments is defined as an asc...
Definition: tensor_cpu-inl.h:590
void set_stream(Stream< Device > *stream)
set the stream to do computation of current tensor
Definition: tensor.h:472
void BatchGEMM(Tensor< Device, 3, DType > dst, const Tensor< Device, 3, DType > &lhs, const Tensor< Device, 3, DType > &rhs, DType alpha, DType beta, Tensor< Device, 1, DType * > workspace)
CPU/GPU: dst = alpha * op(lhs) op(rhs) + beta * dst.
Definition: tensor_cpu-inl.h:611
base class of all rvalues
Definition: expression.h:149
static const bool kDevCPU
whether this device is CPU or not
Definition: tensor.h:42
void DeleteStream(Stream< Device > *stream)
delete the computing stream
MSHADOW_XINLINE Shape< kSubdim > SubShape(void) const
get subshape that takes off largest dimension v *
Definition: tensor.h:170
void MapReduceKeepLowest(TRValue< R, cpu, 1, DType > *dst, const expr::Exp< E, DType, etype > &exp, DType scale=1)
CPU/GPU: map a expression, do reduction to 1D Tensor in lowest dimension (dimension 0) ...
Definition: tensor_cpu-inl.h:224
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape)
Definition: tensor.h:580
#define MSHADOW_ALLOC_PAD
whether do padding during allocation
Definition: base.h:73
device name CPU
Definition: tensor.h:40
device name GPU
Definition: tensor.h:47
MSHADOW_XINLINE Tensor< Device, 2, DType > FlatTo2D(void) const
flatten the tensor to 2 dimension, collapse the higher dimensions together
Definition: tensor.h:520
bool CheckIdle(void)
query whether the the stream is idle
Definition: tensor.h:396
#define MSHADOW_XINLINE
Definition: base.h:223
Tensor< Device, 1, DType > & operator=(const Tensor< Device, 1, DType > &exp)
implement the assignment of same type
Definition: tensor.h:618
MSHADOW_XINLINE Tensor(void)
default constructor
Definition: tensor.h:452
MSHADOW_XINLINE index_t MSize(void) const
Definition: tensor.h:604
definitions of abstract expressions and expressions template
MSHADOW_XINLINE index_t size(index_t i) const
Definition: tensor.h:607
Tensor< Device, dimension, DType > & operator=(const Tensor< Device, dimension, DType > &exp)
implement the assignment of same type
Definition: tensor.h:547
Shape< 3 > ConvertLayout(const Shape< 3 > &src, int src_layout, int dst_layout)
Convert shape in src_layout to shape in dst_layout.
Definition: tensor.h:270
void CreateBlasHandle()
create a blas handle
Definition: tensor.h:400
int32_t index_t
type that will be used for index
Definition: base.h:336
MSHADOW_XINLINE Shape< 1 > FlatTo1D(void) const
Definition: tensor.h:124
MSHADOW_XINLINE Tensor< Device, 1, DType > FlatTo1D(void) const
Definition: tensor.h:590
void AllocSpace(Tensor< cpu, dim, DType > *obj, bool pad=MSHADOW_ALLOC_PAD)
CPU/CPU: allocate space for CTensor, according to the shape in the obj this function is responsible t...
Definition: tensor_cpu-inl.h:117
DType * dptr_
Definition: tensor.h:572
definitions of how expressions should be evaluated
MSHADOW_XINLINE const index_t & operator[](int idx) const
get corresponding index
Definition: tensor.h:99
MSHADOW_XINLINE index_t ProdShape(int dimstart, int dimend) const
Definition: tensor.h:158
definitions of operators in expression with respect to scalar this file will be included several time...
void AddTakeGradLargeBatch(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &sorted, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Gradient accumulate of embedding matrix. dst[sorted[i]] += src[index[i]] Called when the bat...
Definition: tensor_cpu-inl.h:538
MSHADOW_XINLINE Shape< 5 > Shape5(index_t s0, index_t s1, index_t s2, index_t s3, index_t s4)
construct a five dimension shape, stride will equal s0
Definition: tensor.h:256
MSHADOW_XINLINE index_t MemSize(void) const
Definition: tensor.h:480
void SetDevice(int devid)
set the device of current thread to work on
MSHADOW_XINLINE Shape(const Shape< kDimension > &s)
constuctor
Definition: tensor.h:80
some extension of expressions, used to support something beyond elementwise op
MSHADOW_XINLINE Shape< 1 > Shape1(index_t s0)
construct a one dimension shape, stride will equal s0
Definition: tensor.h:207
MSHADOW_XINLINE Tensor< Device, kSubdim, DType > operator[](index_t idx) const
get a element of dimension - 1
Definition: tensor.h:528
index_t shape_[kDimension]
storing the dimension information
Definition: tensor.h:76
MSHADOW_XINLINE Tensor(const Shape< 1 > &shape)
Definition: tensor.h:578
MSHADOW_XINLINE Shape(void)
default constructor, do nothing
Definition: tensor.h:78
void InitTensorEngine(int device_id=0)
initialize tensor engine, used to call intialization functions of dependent libs this function should...
MSHADOW_XINLINE Shape< 2 > Shape2(index_t s0, index_t s1)
construct a two dimension shape, stride will equal s0
Definition: tensor.h:217
implementation of GPU code
MSHADOW_XINLINE bool CheckContiguous(void) const
Definition: tensor.h:601
static const int kDevMask
device flag number, identifies this device
Definition: tensor.h:44
MSHADOW_XINLINE bool CheckContiguous(void) const
Definition: tensor.h:492
MSHADOW_XINLINE Tensor< Device, dimension, DType > Slice(index_t begin, index_t end) const
slice the tensor in highest dimension [begin,end)
Definition: tensor.h:539
void Wait(void)
wait for all the computations associated with this stream to complete
Definition: tensor.h:391
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape, index_t stride, Stream< Device > *stream)
constructor from data pointer and shape
Definition: tensor.h:464
MSHADOW_XINLINE Tensor< Device, 1, DType > Slice(index_t begin, index_t end) const
Definition: tensor.h:596
void MapReduceKeepHighDim(TRValue< R, cpu, 1, DType > *dst, const expr::Exp< E, DType, etype > &exp, DType scale=1)
CPU/GPU: map a expression, do reduction to 1D Tensor in third dimension (dimension 2) ...
Definition: tensor_cpu-inl.h:251
MSHADOW_XINLINE Tensor(const Shape< dimension > &shape)
constructor from shape
Definition: tensor.h:454
index_t stride_
Definition: tensor.h:574
Tensor< Device, dim, DType > NewTensor(const Shape< dim > &shape, DType initv, bool pad=MSHADOW_ALLOC_PAD, Stream< Device > *stream=NULL)
CPU/GPU: short cut to allocate and initialize a Tensor.
Definition: tensor_cpu-inl.h:133
defines how expression exp can be evaluated and stored into dst
Definition: expression.h:80
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape, Stream< Device > *stream)
constructor from data pointer and shape, without stride
Definition: tensor.h:460
Tensor< Device, 1, DType > & operator=(const expr::Exp< E, DType, etype > &exp)
Definition: tensor.h:627
implementation of GPU host code
tensor container that does memory allocation and resize like STL
void AddTakeGrad(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Gradient accumulate of embedding matrix. dst[index[i]] += src[i] Called when the featuredim ...
Definition: tensor_cpu-inl.h:517
MSHADOW_XINLINE Shape< 3 > Shape3(index_t s0, index_t s1, index_t s2)
construct a three dimension shape, stride will equal s0
Definition: tensor.h:228
overloaded + operator between half_t and bf16_t
Definition: base.h:327
void set_stream(Stream< Device > *stream)
Definition: tensor.h:587
Random inline functions for tensor.
MSHADOW_XINLINE DType & operator[](index_t idx)
Definition: tensor.h:610
MSHADOW_XINLINE index_t size(int idx) const
return size of i-th dimension, start counting from highest dimension
Definition: tensor.h:506
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape, index_t stride, Stream< Device > *stream)
Definition: tensor.h:584
index_t stride_
storing the stride information in x dimension this is used to deal with pitch allocation in gpu or ss...
Definition: tensor.h:442
Tensor< Device, 1, DType > & operator=(const DType &exp)
Definition: tensor.h:630
general tensor
Definition: tensor.h:421
implementation of CPU host code
#define MSHADOW_DEFAULT_DTYPE
default data type for tensor string in code release, change it to default_real_t during development...
Definition: base.h:242
MSHADOW_XINLINE Tensor(void)
Definition: tensor.h:577
MSHADOW_XINLINE index_t MSize(void) const
Definition: tensor.h:498
Stream< Device > * stream_
stream where the computation lies stream is a device dependency concept where each computation ...
Definition: tensor.h:447
Shape< 1 > shape_
Definition: tensor.h:573
MSHADOW_XINLINE bool operator==(const Shape< kDimension > &s) const
Definition: tensor.h:106
Tensor< Device, dimension, DType > & operator=(const DType &exp)
functions to fit expression template
Definition: tensor.h:561
computaion stream structure, used for asynchronous computations
Definition: tensor.h:384