12 #ifndef MSHADOW_TENSOR_H_ 13 #define MSHADOW_TENSOR_H_ 44 inline std::ostream &operator<<(std::ostream &os, const Shape<ndim> &shape);
50 template<
int dimension>
53 static const int kDimension = dimension;
55 static const int kSubdim = dimension - 1;
63 for (
int i = 0; i < kDimension; ++i) {
64 this->shape_[i] = s[i];
89 for (
int i = 0; i < kDimension; ++i) {
90 if (s.
shape_[i] != this->shape_[i])
return false;
116 s.
shape_[1] = this->shape_[kDimension - 1];
119 for (
int i = 0; i < kDimension - 1; ++i) {
120 ymax *= this->shape_[i];
127 index_t size = this->shape_[0];
129 for (
int i = 1; i < kDimension; ++i) {
130 size *= this->shape_[i];
142 for (
int i = dimstart; i < dimend; ++i) {
143 num *= this->shape_[i];
155 for (
int i = 0; i < kSubdim; ++i) {
156 s.
shape_[i] = this->shape_[i + 1];
166 template<
int dimstart,
int dimend>
168 Shape<dimend - dimstart> s;
170 for (
int i = dimstart; i < dimend; ++i) {
171 s[i - dimstart] = this->shape_[i];
177 friend std::ostream &operator<<(std::ostream &os, const Shape<dim> &shape);
211 s[0] = s0; s[1] = s1; s[2] = s2;
225 s[0] = s0; s[1] = s1; s[2] = s2; s[3] = s3;
240 s[0] = s0; s[1] = s1; s[2] = s2; s[3] = s3; s[4] = s4;
253 switch (src_layout) {
263 LOG(FATAL) <<
"Invalid layout for 3d shape " << src_layout;
265 switch (dst_layout) {
276 LOG(FATAL) <<
"Invalid layout for 3d shape " << src_layout;
290 switch (src_layout) {
301 LOG(FATAL) <<
"Invalid layout for 4d shape " << src_layout;
305 switch (dst_layout) {
315 LOG(FATAL) <<
"Invalid layout for 4d shape " << src_layout;
330 switch (src_layout) {
342 LOG(FATAL) <<
"Invalid layout for 5d shape " << src_layout;
345 switch (dst_layout) {
356 LOG(FATAL) <<
"Invalid layout for 5d shape " << src_layout;
364 template<
typename Device>
390 template<
typename Container,
typename Device,
int dimension,
typename DType>
400 template<
typename Device,
int dimension,
403 Device, dimension, DType> {
411 static const int kSubdim = dimension - 1;
416 DType *dptr_ =
nullptr;
436 : shape_(shape), stream_(NULL) {}
439 : dptr_(dptr), shape_(shape), stride_(shape[kSubdim]), stream_(NULL) {}
443 : dptr_(dptr), shape_(shape), stride_(shape[kSubdim]), stream_(stream) {}
448 : dptr_(dptr), shape_(shape), stride_(stride), stream_(stream) {}
454 this->stream_ = stream;
460 template<
int startdim>
464 for (
int i = startdim; i < kSubdim; ++i) {
465 memsz *= this->shape_[i];
474 return this->shape_[dimension - 1] == stride_;
480 return this->MemSize<0>();
511 shape_.
SubShape(), stride_, stream_);
524 s, stride_, stream_);
536 template<
typename E,
int etype>
539 return this->__assign(exp);
543 return this->__assign(exp);
549 template<
typename Device,
typename DType>
551 public TRValue<Tensor<Device, 1, DType>, Device, 1, DType> {
560 : shape_(shape), stream_(NULL) {}
562 : dptr_(dptr), shape_(shape), stride_(shape[0]), stream_(NULL) {}
564 : dptr_(dptr), shape_(shape), stride_(shape[0]), stream_(stream) {}
567 : dptr_(dptr), shape_(shape), stride_(stride), stream_(stream) {}
569 this->stream_ = stream;
606 template<
typename E,
int etype>
609 return this->__assign(exp);
612 return this->__assign(exp);
625 template<
typename Device>
633 template<
typename Device>
640 template<
typename Device>
650 template<
typename Device>
652 bool create_dnn_handle,
658 template<
typename Device>
660 return NewStream<Device>(
true,
false, dev_id);
666 template<
typename Device>
679 template<
int dim,
typename DType>
693 template<
int dim,
typename DType>
702 template<
int dim,
typename DType>
710 template<
int dim,
typename DType>
724 template<
typename Device,
typename DType,
int dim>
737 template<
int dim,
typename DType>
749 template<
int dim,
typename DType>
761 template<
int dim,
typename DType>
773 template<
int dim,
typename DType>
782 template<
typename DType>
789 template<
typename DType>
798 template<
typename DType>
808 template<
typename DType>
820 template<
bool clip = true,
typename IndexType,
typename DType>
832 template<
bool clip = true,
typename IndexType,
typename DType>
845 template<
typename IndexType,
typename DType>
859 template<
typename IndexType,
typename DType>
872 template<
typename IndexType,
typename DType>
884 template<
typename IndexType,
typename DType>
894 template<
typename KDType,
typename VDType>
896 bool is_ascend =
true);
903 template<
typename KDType,
typename VDType>
905 bool is_ascend =
true);
914 template<
typename Device,
typename VDType,
typename SDType>
931 template<
typename Saver,
typename R,
int dim,
932 typename DType,
typename E,
int etype>
947 template<
typename Saver,
typename R,
int dim,
948 typename DType,
typename E,
int etype>
964 template<
typename Saver,
typename Reducer,
965 typename R,
typename DType,
typename E,
int etype>
982 template<
typename Saver,
typename Reducer,
typename R,
983 typename DType,
typename E,
int etype>
1001 template<
typename Saver,
typename Reducer,
int dimkeep,
1002 typename R,
typename DType,
typename E,
int etype>
1020 template<
typename Saver,
typename Reducer,
int dimkeep,
1021 typename R,
typename DType,
typename E,
int etype>
1031 template<
typename Device,
typename DType>
1044 template<
bool transpose_left,
bool transpose_right,
typename Device,
typename DType>
1062 #ifdef MSHADOW_SCALAR_ 1063 #error "MSHADOW_SCALAR_ must not be defined" 1066 #define MSHADOW_SCALAR_ float 1068 #undef MSHADOW_SCALAR_ 1069 #define MSHADOW_SCALAR_ double 1071 #undef MSHADOW_SCALAR_ 1072 #define MSHADOW_SCALAR_ int32_t 1074 #undef MSHADOW_SCALAR_ 1075 #define MSHADOW_SCALAR_ int64_t 1077 #undef MSHADOW_SCALAR_ 1078 #define MSHADOW_SCALAR_ mshadow::half::half_t 1080 #undef MSHADOW_SCALAR_ 1081 #endif // MSHADOW_TENSOR_H_ void VectorDot(Tensor< Device, 1, DType > dst, const Tensor< Device, 1, DType > &lhs, const Tensor< Device, 1, DType > &rhs)
CPU/GPU: 1 dimension vector dot.
Definition: tensor_cpu-inl.h:576
void FreeSpace(Tensor< cpu, dim, DType > *obj)
CPU/GPU: free the space of tensor, will set obj.dptr to NULL.
Definition: tensor_cpu-inl.h:122
Stream< Device > * stream_
Definition: tensor.h:556
MSHADOW_XINLINE index_t & operator[](int idx)
get corresponding index
Definition: tensor.h:72
void IndexFill(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Fill the values of the destination matrix to specific rows in the source matrix...
Definition: tensor_cpu-inl.h:526
void SoftmaxGrad(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 2, DType > &src, const Tensor< cpu, 1, DType > &label)
CPU/GPU: softmax gradient.
Definition: tensor_cpu-inl.h:288
PaddingExp< SrcExp, DType, ExpInfo< SrcExp >::kDim > pad(const Exp< SrcExp, DType, etype > &src, index_t pad)
padding expression, pad a image with zeros on boundaries, padding affects shape[0], and shape[1]
Definition: pad.h:53
MSHADOW_XINLINE index_t Size(void) const
Definition: tensor.h:126
DType * dptr_
pointer to the data
Definition: tensor.h:416
Tensor RValue, this is the super type of all kinds of possible tensors.
Definition: tensor.h:391
Stream< Device > * NewStream(bool create_blas_handle, bool create_dnn_handle, int dev_id=-1)
create a new stream from system
MSHADOW_XINLINE Shape< dimend-dimstart > Slice(void) const
slice the shape from start to end
Definition: tensor.h:167
MSHADOW_XINLINE Tensor< Device, 2, DType > FlatTo2D(void) const
Definition: tensor.h:574
void Copy(Tensor< cpu, dim, DType > dst, const Tensor< cpu, dim, DType > &src, Stream< cpu > *stream=NULL)
copy data from one tensor to another, with same shape
Definition: tensor_cpu-inl.h:127
void ShutdownTensorEngine(void)
Shutdown tensor engine on current device this function should be called after all GPU tensor operatio...
shape of a tensor
Definition: tensor.h:35
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape, Stream< Device > *stream)
Definition: tensor.h:563
void MapExp(TRValue< R, cpu, dim, DType > *dst, const expr::Exp< E, DType, etype > &exp)
CPU/GPU: map a expression to a tensor, this function calls MapPlan.
Definition: tensor_cpu-inl.h:189
Definition: stream_gpu-inl.h:19
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape)
constructor from data pointer and shape, without stride
Definition: tensor.h:438
MSHADOW_XINLINE Tensor< Device, 1, DType > FlatTo1D(void) const
flatten the tensor to 1 dimension
Definition: tensor.h:494
Shape< dimension > shape_
shape of the tensor
Definition: tensor.h:418
MSHADOW_XINLINE const DType & operator[](index_t idx) const
Definition: tensor.h:594
MSHADOW_XINLINE Shape< 4 > Shape4(index_t s0, index_t s1, index_t s2, index_t s3)
construct a four dimension shape, stride will equal s0
Definition: tensor.h:222
MSHADOW_XINLINE bool operator!=(const Shape< kDimension > &s) const
Definition: tensor.h:98
void SortByKey(Tensor< cpu, 1, KDType > keys, Tensor< cpu, 1, VDType > values, bool is_ascend=true)
CPU/GPU: Sort key-value pairs stored in separate places. (Stable sort is performed!) ...
Definition: tensor_cpu-inl.h:537
Tensor< Device, dimension, DType > & operator=(const expr::Exp< E, DType, etype > &exp)
functions to fit expression template
Definition: tensor.h:538
MSHADOW_XINLINE Shape< 2 > FlatTo2D(void) const
Definition: tensor.h:114
void Softmax(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 2, DType > &energy)
CPU/GPU: normalize softmax: dst[i][j] = exp(energy[i][j]) /(sum_j exp(energy[i][j])) ...
Definition: tensor_cpu-inl.h:465
void VectorizedSort(Tensor< Device, 1, VDType > values, Tensor< Device, 1, SDType > segments)
CPU/GPU: Sort the keys within each segment. (Stable sort is performed!) Segments is defined as an asc...
Definition: tensor_cpu-inl.h:568
void set_stream(Stream< Device > *stream)
set the stream to do computation of current tensor
Definition: tensor.h:453
void BatchGEMM(Tensor< Device, 3, DType > dst, const Tensor< Device, 3, DType > &lhs, const Tensor< Device, 3, DType > &rhs, DType alpha, DType beta, Tensor< Device, 1, DType * > workspace)
CPU/GPU: dst = alpha * op(lhs) op(rhs) + beta * dst.
Definition: tensor_cpu-inl.h:589
base class of all rvalues
Definition: expression.h:130
static const bool kDevCPU
whether this device is CPU or not
Definition: tensor.h:23
void DeleteStream(Stream< Device > *stream)
delete the computing stream
MSHADOW_XINLINE Shape< kSubdim > SubShape(void) const
get subshape that takes off largest dimension v *
Definition: tensor.h:151
void MapReduceKeepLowest(TRValue< R, cpu, 1, DType > *dst, const expr::Exp< E, DType, etype > &exp, DType scale=1)
CPU/GPU: map a expression, do reduction to 1D Tensor in lowest dimension (dimension 0) ...
Definition: tensor_cpu-inl.h:205
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape)
Definition: tensor.h:561
#define MSHADOW_ALLOC_PAD
whether do padding during allocation
Definition: base.h:54
device name CPU
Definition: tensor.h:21
device name GPU
Definition: tensor.h:28
MSHADOW_XINLINE Tensor< Device, 2, DType > FlatTo2D(void) const
flatten the tensor to 2 dimension, collapse the higher dimensions together
Definition: tensor.h:501
bool CheckIdle(void)
query whether the the stream is idle
Definition: tensor.h:377
#define MSHADOW_XINLINE
Definition: base.h:204
Tensor< Device, 1, DType > & operator=(const Tensor< Device, 1, DType > &exp)
implement the assignment of same type
Definition: tensor.h:599
MSHADOW_XINLINE Tensor(void)
default constructor
Definition: tensor.h:433
MSHADOW_XINLINE index_t MSize(void) const
Definition: tensor.h:585
definitions of abstract expressions and expressions template
MSHADOW_XINLINE index_t size(index_t i) const
Definition: tensor.h:588
Tensor< Device, dimension, DType > & operator=(const Tensor< Device, dimension, DType > &exp)
implement the assignment of same type
Definition: tensor.h:528
Shape< 3 > ConvertLayout(const Shape< 3 > &src, int src_layout, int dst_layout)
Convert shape in src_layout to shape in dst_layout.
Definition: tensor.h:251
void CreateBlasHandle()
create a blas handle
Definition: tensor.h:381
int32_t index_t
type that will be used for index
Definition: base.h:291
MSHADOW_XINLINE Shape< 1 > FlatTo1D(void) const
Definition: tensor.h:105
MSHADOW_XINLINE Tensor< Device, 1, DType > FlatTo1D(void) const
Definition: tensor.h:571
void AllocSpace(Tensor< cpu, dim, DType > *obj, bool pad=MSHADOW_ALLOC_PAD)
CPU/CPU: allocate space for CTensor, according to the shape in the obj this function is responsible t...
Definition: tensor_cpu-inl.h:98
DType * dptr_
Definition: tensor.h:553
definitions of how expressions should be evaluated
MSHADOW_XINLINE const index_t & operator[](int idx) const
get corresponding index
Definition: tensor.h:80
MSHADOW_XINLINE index_t ProdShape(int dimstart, int dimend) const
Definition: tensor.h:139
definitions of operators in expression with respect to scalar this file will be included several time...
void AddTakeGradLargeBatch(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &sorted, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Gradient accumulate of embedding matrix. dst[sorted[i]] += src[index[i]] Called when the bat...
Definition: tensor_cpu-inl.h:516
MSHADOW_XINLINE Shape< 5 > Shape5(index_t s0, index_t s1, index_t s2, index_t s3, index_t s4)
construct a five dimension shape, stride will equal s0
Definition: tensor.h:237
MSHADOW_XINLINE index_t MemSize(void) const
Definition: tensor.h:461
void SetDevice(int devid)
set the device of current thread to work on
MSHADOW_XINLINE Shape(const Shape< kDimension > &s)
constuctor
Definition: tensor.h:61
some extension of expressions, used to support something beyond elementwise op
MSHADOW_XINLINE Shape< 1 > Shape1(index_t s0)
construct a one dimension shape, stride will equal s0
Definition: tensor.h:188
MSHADOW_XINLINE Tensor< Device, kSubdim, DType > operator[](index_t idx) const
get a element of dimension - 1
Definition: tensor.h:509
index_t shape_[kDimension]
storing the dimension information
Definition: tensor.h:57
MSHADOW_XINLINE Tensor(const Shape< 1 > &shape)
Definition: tensor.h:559
MSHADOW_XINLINE Shape(void)
default constructor, do nothing
Definition: tensor.h:59
void InitTensorEngine(int device_id=0)
initialize tensor engine, used to call intialization functions of dependent libs this function should...
MSHADOW_XINLINE Shape< 2 > Shape2(index_t s0, index_t s1)
construct a two dimension shape, stride will equal s0
Definition: tensor.h:198
implementation of GPU code
MSHADOW_XINLINE bool CheckContiguous(void) const
Definition: tensor.h:582
static const int kDevMask
device flag number, identifies this device
Definition: tensor.h:25
MSHADOW_XINLINE bool CheckContiguous(void) const
Definition: tensor.h:473
MSHADOW_XINLINE Tensor< Device, dimension, DType > Slice(index_t begin, index_t end) const
slice the tensor in highest dimension [begin,end)
Definition: tensor.h:520
void Wait(void)
wait for all the computations associated with this stream to complete
Definition: tensor.h:372
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape, index_t stride, Stream< Device > *stream)
constructor from data pointer and shape
Definition: tensor.h:445
MSHADOW_XINLINE Tensor< Device, 1, DType > Slice(index_t begin, index_t end) const
Definition: tensor.h:577
void MapReduceKeepHighDim(TRValue< R, cpu, 1, DType > *dst, const expr::Exp< E, DType, etype > &exp, DType scale=1)
CPU/GPU: map a expression, do reduction to 1D Tensor in third dimension (dimension 2) ...
Definition: tensor_cpu-inl.h:232
MSHADOW_XINLINE Tensor(const Shape< dimension > &shape)
constructor from shape
Definition: tensor.h:435
index_t stride_
Definition: tensor.h:555
Tensor< Device, dim, DType > NewTensor(const Shape< dim > &shape, DType initv, bool pad=MSHADOW_ALLOC_PAD, Stream< Device > *stream=NULL)
CPU/GPU: short cut to allocate and initialize a Tensor.
Definition: tensor_cpu-inl.h:114
defines how expression exp can be evaluated and stored into dst
Definition: expression.h:61
MSHADOW_XINLINE Tensor(DType *dptr, const Shape< dimension > &shape, Stream< Device > *stream)
constructor from data pointer and shape, without stride
Definition: tensor.h:441
Tensor< Device, 1, DType > & operator=(const expr::Exp< E, DType, etype > &exp)
Definition: tensor.h:608
implementation of GPU host code
tensor container that does memory allocation and resize like STL
void AddTakeGrad(Tensor< cpu, 2, DType > dst, const Tensor< cpu, 1, IndexType > &index, const Tensor< cpu, 2, DType > &src)
CPU/GPU: Gradient accumulate of embedding matrix. dst[index[i]] += src[i] Called when the featuredim ...
Definition: tensor_cpu-inl.h:498
MSHADOW_XINLINE Shape< 3 > Shape3(index_t s0, index_t s1, index_t s2)
construct a three dimension shape, stride will equal s0
Definition: tensor.h:209
namespace for mshadow
Definition: base.h:282
void set_stream(Stream< Device > *stream)
Definition: tensor.h:568
Random inline functions for tensor.
MSHADOW_XINLINE DType & operator[](index_t idx)
Definition: tensor.h:591
MSHADOW_XINLINE index_t size(int idx) const
return size of i-th dimension, start counting from highest dimension
Definition: tensor.h:487
MSHADOW_XINLINE Tensor(DType *dptr, Shape< 1 > shape, index_t stride, Stream< Device > *stream)
Definition: tensor.h:565
index_t stride_
storing the stride information in x dimension this is used to deal with pitch allocation in gpu or ss...
Definition: tensor.h:423
Tensor< Device, 1, DType > & operator=(const DType &exp)
Definition: tensor.h:611
general tensor
Definition: tensor.h:402
implementation of CPU host code
#define MSHADOW_DEFAULT_DTYPE
default data type for tensor string in code release, change it to default_real_t during development...
Definition: base.h:223
MSHADOW_XINLINE Tensor(void)
Definition: tensor.h:558
MSHADOW_XINLINE index_t MSize(void) const
Definition: tensor.h:479
Stream< Device > * stream_
stream where the computation lies stream is a device dependency concept where each computation ...
Definition: tensor.h:428
Shape< 1 > shape_
Definition: tensor.h:554
MSHADOW_XINLINE bool operator==(const Shape< kDimension > &s) const
Definition: tensor.h:87
Tensor< Device, dimension, DType > & operator=(const DType &exp)
functions to fit expression template
Definition: tensor.h:542
computaion stream structure, used for asynchronous computations
Definition: tensor.h:365